The present invention relates to the field of comparators. More specifically, one embodiment of the invention provides an improved sample-and-hold comparator which can amplify a signal at high-speed.
Using latches for amplifying digital signals are known. One such latch, a "Yang" latch, is described in CK. Yang, M. Horowitz, "A 0.8-um CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2015-23 (December, 1996). The Yang latch uses aggressive equalization to handle intersymbol interference. A disadvantage to the Yang latch is that the aggressive equalization loads additional capacitance on the output and thereby reduces the effective bandwidth of the latch. Additionally, the Yang latch requires complementary clocks and thus raises the problem of trying to maintain tight timing margins between the complementary clock signals.
A. Fiedler, et al., "A 1.0625 Gbps Transceiver with 2.times.Oversampling and Transmit Signal Pre-Emphasis," ISSCC Dig. Tech. Papers, pp. 238-39 (February, 1997) describes another latch which does use a single clock phase to control a regenerative amplify mechanism in series with an input differential pair, but results in an increased metastability window since the input data is allowed to move during a amplification period.
From the above it is seen that an improved comparator for use in a sample-and-hold latch is needed.